Integrated circuits of this type include a considerable number of electronic components produced in the silicon wafer. These electronic components are activated by making metal contacts on the various active regions of said components. These contacts are connected to the contacts of the other components by interconnections in order to make the integrated circuits capable of functioning. Thus, for example, in order to activate a bipolar transistor, contacts must be made on the collector, base and emitter regions; and in order to activate a (MOS) field-effect transistor, contacts must be made on the source and drain regions and on the polycrystalline silicon gate.
The contacts and interconnections in an integrated circuit may not only be metal but also made of a metal silicide, in particular a refractory metal silicide.
The regions on which these contacts and interconnections are to be produced are subjected to metallization. The silicon regions to be metallized are referred to as bare silicon regions, as opposed to the other silicon regions of the wafer which are covered by an insulator, in particular by silicon oxide. The bare silicon regions can be metallized using various methods, for example depositing a refractory metal silicide.
Although keeping a general scope, the invention will be described more particularly with reference to the metallization of integrated circuit silicon semiconductor devices including (MOS) field-effect transistors in technologies with design rules of less than 0.5 .mu.m, commonly referred to as sub-0.5 .mu.m technologies. These technologies more precisely correspond to a length of less than 0.5 .mu.m for the channel separating the source and drain regions of the transistor. These very small transistors make it possible to produce integrated circuits with high integration level which are of great interest in microelectronics, for example integrated circuits of the VLSI and ULSI type.
In sub-0.5 .mu.m technologies, the source and drain junctions are located at about 0.1 .mu.m below the surface of the bare silicon. In order to ensure that these transistors, and therefore the integrated circuit, function properly these shallow source and drain junctions must be preserved when making contacts.
Furthermore, acceptable metallization of the bare silicon regions for integrated circuits with high integration level must generate a uniform deposit in which the grain size of the deposited particles is sufficiently small for the surface of the deposited layer to have little roughness. These characteristics are essential for proper functioning of integrated circuits fabricated in sub-0.5 .mu.m technologies.
Various prior art processes make it possible to deposit refractory metal silicides on bare silicon.
In particular, it is known from U.S. Pat. No. 4,619,038 to metallize the source and drain regions, as well as the polycrystalline silicon gate of a field-effect transistor using a first deposit of a titanium silicide layer, by placing the silicon wafer, partially masked by silicon oxide, in an enclosure comprising, as the reactive gas, a titanium halide diluted in hydrogen. A titanium silicide layer is thus formed on the bare monocrystalline and polycrystalline silicon regions at temperatures of between 700.degree. and 1000.degree. C.
When this process is implemented, a large amount of bare silicon is found to be consumed, which entails serious consequences since the titanium silicide will penetrate deeply into the regions to be metallized. This leads to a significant risk of the junctions being pierced, in particular the shallow source and drain junctions which are located at about 0.1 .mu.m below the surface of the bare silicon in sub-0.5 .mu.m technologies.
This method has the additional drawback of a deposit having a high degree of surface roughness. These defects of the titanium silicide deposit are deemed unacceptable, in particular in the sub-0.5 .mu.m technologies mentioned above.
Another U.S. Pat. No., 4,501,769, describes a process for selectively depositing a refractory metal silicide on monocrystalline and polycrystalline silicon, which employs a mixture of reactive gases comprising a silicon precursor gas. The purpose of this mixture of reactive gases is to prevent consumption of the bare silicon of the substrate on which the selective deposition takes place.
However, deposition of this type requires a reaction temperature of about 850.degree. C., at which temperature, in the presence of the refractory metal precursor, reaction with the bare silicon of the wafer is inevitable. The risk of the junctions being pierced cannot therefore be completely eliminated when the process is applied to field-effect transistors, in particular in the sub-0.5 .mu.m technologies.
Furthermore, the silicide layers formed when using the process described in U.S. Pat. No. 4,501,769 have a large grain size and therefore a high degree of surface roughness, which characteristic is deemed unacceptable for the intended applications as described above.
French Patent Application 2 623 014 describes a method for selectively depositing a refractory metal silicide, which proposes to overcome such drawbacks constituted by the high degree of surface roughness and the consumption of bare silicon.
According to the process which is described, the wafers are deoxidized during a first step, referred to as a cleaning step. This cleaning step consists in refractory metal silicide deposition, with a stoichiometric excess of silicon, by heating a gas mixture of silane, titanium tetrachloride, argon and hydrogen to a temperature of between 800.degree. C. and 1000.degree.. This deposition with a stoichiometric excess of silicon is intended to suppress the native oxide SiO.sub.2 which is formed on the silicon regions to be metallized. In a second step, at a lower temperature, between 450.degree. C. and 700.degree. C., a refractory metal silicide layer, with a stoichiometric amount of silicon, is deposited in the presence of the same gas mixture but at different partial pressures.
The first step seems to obtain a lower degree of surface roughness for the TiSi.sub.2 deposited. This result can be interpreted by elimination of the native oxide, the presence of which would interfere with the selective deposition of titanium silicide. Indeed, it seems that the selectivity of the deposition and the presence of native oxide promotes deposition in islands, firstly starting in the nucleation regions which are free of native oxide. Deposition of this type generates coarse-grain layers with a high degree of surface roughness.
The second step, the deposition step proper, is carried out with the aim of limiting the consumption of bare silicon which could take place in the presence of titanium tetrachloride.
The authors of the present invention have observed that, when the process described in Patent Application FR 2 623 014 is implemented, consumption of the bare silicon persists. Therefore, for applications in the technologies mentioned above, the risk of the shallow junctions being pierced remains. Furthermore, the refractory metal silicide layer which is formed still includes surface defects, such as grains which are excessively large and a degree of surface roughness which is too great for use in sub-0.5 .mu.m technologies with high integration level.
Furthermore, the authors of the present invention have also demonstrated that the titanium silicide layer obtained using this method is formed by two different crystallographic phases of titanium silicide, one of which has a resistivity which is much too great for application to the fabrication of integrated circuits with a high integration level. Indeed, circuits of the VLSI type have their performance considerably restricted when the resistivity of the contact and interconnection levels is too high.
French Patent Application No. 94 09819 describes a process for selective vapor deposition of a silicide of a refractory metal on the monocrystalline and polycrystalline silicon of a silicon wafer, comprising the following steps:
(i) a cleaning step intended to prepare the silicon surface for the deposition, by making it free not only of native oxide but also of all other residues and impurities present at the surface of the silicon; PA1 (ii) a step of depositing a silicon layer in order to form a silicon pedestal on the actual monocrystalline and polycrystalline silicon of the wafer; and PA1 (iii) a step of vapor deposition of a refractory metal silicide, at least partially consuming the silicon pedestal formed during the preceding step. PA1 a step of preparing said surface, consisting in forming a layer, of thickness e.ltoreq.1 nm, of silicon oxide or silicon oxynitride on this surface; and PA1 a step of selective chemical vapor deposition (CVD), on the silicon oxide or oxynitride layer, of a refractory metal silicide. PA1 it should block the progression of the growth of the refractory metal silicide during the step of depositing this silicide and, in particular, it should not evaporate during the deposition of the refractory metal silicide by CVD, for example under the reducing action of the hydrogen or the SiH.sub.4 which are used in this step; PA1 it should be reproducible; PA1 it should be thin enough not to act as a thick oxide surface, such as a thick SiO.sub.2 surface, in which case there would not be selective refractory metal silicide deposition.
This process makes it possible to control the consumption of the silicon of the wafer because it appears that the silicon pedestal provided by step (ii) is at least partially, if not completely, consumed in order to form the layer of the refractory metal silicide; the bare silicon of the wafer is thus protected by the pedestal during the deposition in step (iii).
It furthermore appears that the deposit thus obtained on a silicon surface free of native oxide and all types of residues and impurities makes it possible to grow small grains, leading to a uniform layer, with a low degree of surface roughness, which is compatible with sub-0.5 .mu.m technologies, such as those with a high integration level.
In order to rid the silicon surface to be metallized of native oxide and all the residues and impurities due, in particular, to the technological treatments to which the wafer may already have been subjected, for example etching or implantation, which in particular leave carbon residues, cleaning methods are used, the selection of which depends on these prior technological treatments. Cleaning methods which can be used are, in particular, cleaning methods assisted by plasma (soft-etch), by sacrificial oxide (5 to 45 nm), by the two consecutive methods, by chemical treatment, for example by treatment of the RCA type, by the action of dilute HF or by these two consecutive methods, or by any other suitable method which leaves the silicon surface free of residues, impurities and native oxide.
When the wafers have been subjected to certain prior technological treatments, it is possible that the silicon surfaces thus cleaned may not be entirely free of residues. The silicide deposition on a surface of this type could take place in islands and thus form a coarse-grained rough layer.
Application FR-A-94 09819 more particularly proposes to supplement this first cleaning phase with a second surface preparation phase referred to as "in situ" preparation since it may take place in the same reactor as the silicon layer deposition step (ii). As opposed to this, the first phase of the cleaning step, described above, is referred to as "ex situ" cleaning.
The fundamental utility of in situ preparation of this type consists in obtaining a deposit which meets specifications such as a low access resistance and continuity between two n and p doped regions. A surface which is as perfect as possible is thus obtained before the epitaxial Si deposition, followed by the TiSi.sub.2 chemical vapor deposition (CVD).
Although satisfactory results have been obtained with the technique described in Application FR-94 09819, a tendency to the junctions being pierced has been observed, or in terms of materials, a growth of TiSi.sub.2 propagating through the substrate by consuming the Si of the substrate, thus piercing the junctions. In spite of the formation of the silicon pedestal, and in spite of the supply of silicon by the gas phase (SiH.sub.4 +TiCl.sub.4), such a tendency to the junctions being pierced is observed.
The influence of the presence of a controlled-thickness oxide layer for the fabrication of certain semiconductor devices has also been studied.
Thus, the article entitled "Application of a Cluster Tool for Interface Engineering of Polysilicon Emitters" R. H. Reuss, C. Werkhoven, E. Granneman, M. Hendricks, IEEE 1993 Bipolar Circuits and Technology Meeting 3.4, CH3315-9/93/0000(0049)$1.00.COPYRGT. 1993 IEEE describes the production of a high-quality ultrathin oxide layer using a high-temperature oxidation process before depositing polysilicon to form the emitter of a bipolar transistor in a cluster tool. This article mentions that a high current gain is obtained, but that the resistance of the emitter is detrimentally affected.
Consideration has also be given to forming a subnanometric oxide layer between a polysilicon deposit and a doped substrate in a cluster tool. The presence of the subnanometric oxide layer makes it possible to adjust the current gain of high-speed poly-emitter bipolar transistors to the desired values while simultaneously reducing the contact resistance of the collector.
Finally, it has been suggested to obtain subnanometric layers of silicon oxide by ozonizing, and of silicon oxynitride by treating silicon wafers with NO in order to promote the subsequent deposition of a polysilicon layer.